Contemporary field-programmable gate arrays (FPGAs) have large resources of
logic gates and RAM blocks to implement complex digital computations. As FPGA designs employ very fast I/O rates and bidirectional data
buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time.
Floor planning enables resource allocation within FPGAs to meet these time constraints. FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping,
partial re-configuration of a portion of the design
 and the low non-recurring engineering costs relative to an
ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.
Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable
slew rate on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise
couple unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly.
 Also common are quartz-
crystal oscillators, on-chip resistance-capacitance oscillators, and
phase-locked loops with embedded
voltage-controlled oscillators used for clock generation and management and for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential
comparators on input pins designed to be connected to
differential signaling channels. A few "
mixed signal FPGAs" have integrated peripheral
analog-to-digital converters (ADCs) and
digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a
 Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and
field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.